1. Field of the Invention
This invention pertains generally to semiconductor memory, and more particularly to dynamic memory having a static memory interface.
2. Description of Related Art
Static random access memory (SRAM) circuits provide high speed data access while retaining data as long as power is retained on the circuit. Static RAM cell structures, however, typically require at least six transistors which limit the number of memory cells which can be fabricated on a die of a given size.
Dynamic RAM (DRAM), on the other hand, can be very densely packed because only a single transistor and capacitor is required per memory cell. However, dynamic RAM requires additional support circuitry and has other characteristics which limit its use. For example, the access time of the fastest dynamic memory is typically much slower than for fast static memory, since reading the state of the cell requires a period of time to allow sufficient charge from the small storage capacitance to be stored on the capacitance of the read circuit. In addition, reading from dynamic memory is destructive, wherein a write, or restore, operation must follow each read operation. Furthermore, periodic refreshing of the cell states is required so that data is not lost in response to leakage currents changing the stored voltage value. These restore and refresh operations increase the maximum access times to memory as it is unavailable during restore and refresh.
Dynamic memories in many cases have been implemented with internal refresh circuitry that attempts to hide the dynamic nature of the devices. The idea being that with the refresh and rewrite issues hidden by interface logic, the DRAM can appear to a circuit as if it is SRAM. These DRAM devices which appear substantially similar to SRAM devices are often referred to as 1T1C SRAM devices, which is a label indicative of their dynamic memory nature.
Using DRAM which operates similar to SRAM is attractive in that DRAM, even including the overhead of internal refresh logic can be fabricated in less die area than is required for SRAM. The 1T1C (1 Transistor 1 Capacitor) SRAM is a memory type which provides high memory density while incorporating SRAM similar interfacing. Yet, a number of compatibility issues remain with regard to using 1T1C SRAM in place of conventional SRAM.
(a) Invalid address issue.
Memory addresses for SRAM devices are always valid, unlike DRAM devices for which “invalid address” conditions can occur. Since SRAM chips have no need for the restore and refresh operations the requested output is always available. However, in DRAM, when the address is valid for an insufficient time to allow for the restore operation, the output cannot be generated and the cell information will be lost.
FIG. 1 depicts timing for different address periods. As shown in the figure, after chip select goes active (signal CSB going low), the duration of the memory address can vary. However, depending on the address duration period, several problems can occur in using 1T1C SRAM that result in an invalid address.
(i) Short address valid period: When the duration of the address is shorter than the minimum tRC, insufficient time is provided for the cell data to be restored (A). The minimum tRC is the minimum time needed required time to complete a DRAM operation read operation including a charge restoring operation.
(ii) Long address valid period: When the duration of the address is of sufficient length to complete any DRAM operation without causing any problems (B).
(iii) Excessively long address period: When the duration of the address is too long, typically longer than a few microseconds, the boosting level of a word line signal can be lowered and the cell restoring level can be degraded.
(b) Refresh hiding issue.
Since the 1T1C SRAM has the SRAM interface, control signals are not received for activating a refresh operation as in conventional DRAM even though the cell refresh operation is required since the DRAM leaky cell is used. The internal circuitry performs the refresh operations. However, the accesses to the cells for the purpose of refresh can be generated at any time, such as shown in FIG. 2.
(c) Page mode issue.
A fast access mode, referred to as a page cycle mode, can be utilized in which data is accessed in the same row without changing a row address thereby improving the performance of 1T1C SRAM. FIG. 3 depicts timing for a page mode 1T1C SRAM. The first data is fetched within the tRC time delay but the second data in the same row is fetched in the time period tPC which is typically much shorter than period tRC.
It will be appreciated, therefore, that many of the DRAM issues can pose a problem for the associated circuitry. These issues are typically handled by modifying the device specification sheet to guarantee 1T1C SRAM device operation, thus masking the invalid address and refresh hiding issues. That is, some restrictions are posed on 1T1C SRAM control timing which fall short of providing full compatibility with SRAM chips, and thereby limit the applicability of these memory devices. The following outlines typical restrictions which are posed on accessing 1T1C SRAM devices.
(a) Restrictions are specified to ensure sufficient address set-up and hold time for detecting the valid address. The restriction attempts to overcome the invalid address issue, however, it enforces unnecessarily extended timing margins for set-up and hold time which are not otherwise necessary for the vast majority of memory accesses.
(b) Restrictions are also specified to ensure that the address is available for a sufficient period of time to satisfy the underlying DRAM limitations. This approach, however, still does not provide full compatibility with true SRAM devices, and burdens the circuit with additional memory access limitations.
(c) Restrictions are imposed on address skew which are often quite strict.
(d) Restrictions are imposed on timing instances to be avoided so as to prevent erroneous memory operation.
FIG. 4 depicts a conventional pulsed word line scheme within a 1T1C SRAM memory device. Access commands (i.e. read or write) and/or address are being received by the Address Buffer and Command Buffer. The ATD Generator detects address transitions while the CMD Generator generates commands. In response to the ATD Generator and CMD Generator an Addi block generates a valid address internally. A Decoder decodes the valid internal address and a Block coding block selects valid memory array blocks. A Sensing control block generates BLSA (Bit Line Sense Amplifier) control signals and other related signals.
A WL Generator (word line generator) operates to enable the word line of the DRAM cell array. An S/A enable block generates a BLSA enable signal.
During read or write operations a Delay Circuit block creates guaranteed delay times for cell restore, while an End of restore block creates an (EOR) end of restore signal. The EOR signal disables the word line and the Sensing control block signals when the read or write access operation is finished. The chip then enters a stand-by mode.
FIG. 5 is a block diagram of a conventional refresh scheme. Accesses are being performed (read or write) and the Address Buffer, Command Buffer, ATD Generator, CMD Generator and Addi are operating as described for FIG. 4. An Active & refresh Arbitrator block determines whether to perform a read or write operation or a refresh operation. The following cases can arise when a Refresh control block request refresh operation.
Case 1—In this case the chip is in a stand-by mode and refresh is performed.
Case 2—In this case the chip is performing a read or write operation, wherein the refresh operation is delayed until the read or write operation is completed.
Case 3—In this case the read or write command conflicts with the refresh request, wherein Arbitrator decides order.
The Decoder block decodes valid internal addresses and the Block coding block selects valid memory array blocks.
FIG. 6 is a block diagram of a conventional late write scheme. Accesses are being performed (read or write) and the Address Buffer, Command Buffer, ATD Generator, CMD Generator and Addi are operating as described for FIG. 4 and FIG. 5. In response to a write command the present address is latched in the Add. Latch block and the present data is latched in the Data in Latch block. If the chip was previously performing a write command, the Addi block generates a valid address internally (i.e. it is N−1 write addresses from the latch). If the chip did not perform a prior write command, then no more operation will be performed. If the chip was previously performing a write command, then the Write Driver block drives write (data in) data (i.e. it is N−1 data in from latch).
The Row Decoder block decodes valid internal addresses for Row(WL) selection by WL Generator block. The Column Decoder block decodes valid internal addresses for Column(CSL) selection by CSL Generator. The WL Generator block enables the word line. The End of Restore (EOR) block (not shown) disables WL and the Sensing control signals when write operation is finished. The chip then enters a stand-by status.
Accordingly, the present DRAM devices (1T1C SRAM) which attempt to simulate conventional SRAM devices have a number of drawbacks which limit access speed and applicability and which are not fully compatible with conventional SRAM devices, thus complicating memory interfacing and use. The present invention overcomes these deficiencies, as well as others, of previously developed 1T1C SRAM interfacing solutions and provides a number of benefits.